Compute efficiency and energy efficiency are more than ever major concerns for future Exascale systems.
Since October 2011, the aim of the European project called Mont-Blanc has been to design a new type of computer architecture capable of setting future global HPC standards, built from energy efficient ARM solutions initially used in embedded and mobile devices. Phases 1 and 2 of the project were coordinated by the Barcelona Supercomputing Center (BSC). Phase 1 had a budget of over 14 million, including over 8 million Euros funded by the European Commission. Two years later, the European Commission granted additional 8 million Euro funds to extend the Mont-Blanc project activities until September 2016.

This three year extension enabled further development of the OmpSs parallel programming model to automatically exploit multiple cluster nodes, transparent application check pointing for fault tolerance, support for ARMv8 64-bit processors, and the initial design of the Mont-Blanc Exascale architecture.

The third phase of the Mont-Blanc project started in October 2015: it is coordinated by Bull, an Atos company, and has a budget of 7.9 million Euros, funded by the European Commission under the Horizon 2020 programme. The third phase adopts a co-design approach to ensure that hardware and system innovations are readily translated into benefits for HPC applications. It aims at designing a new high-end HPC platform that is able to deliver a new level of performance / energy ratio when executing real applications.