Blade fully populated with SDB

From 2011 - 2015, the Mont-Blanc had the three following objectives:

  • To develop a full energy-efficient HPC prototype using low-power commercially available embedded technology.
  • To design a next-generation HPC system together with a range of embedded tchnologies in order to overcome the limitations identified in the prototype system.
  • To develop a portfolio of exascale applications to be run on this new generation of HPC systems.

This will produce a new type of computer architecture capable of setting future global HPC standards that will provide Exascale performance using 15 to 30 times less energy.

From 2013 - 2016, the extension of the project has the following three objectives:

  • To complement the effort on the Mont-Blanc system software stack, with emphasis on programmer tools (debugger, performance analysis), system resiliency (from applications to architecture support), and ARM 64-bit support
  • To produce a first definition of the Mont-Blanc Exascale architecture, exploring different alternatives for the compute node (from low-power mobile sockets to special-purpose high-end ARM chips), and its implications on the rest of the system
  • To track the evolution of ARM-based systems, deploying small cluster systems to test new processors that were not available for the original Mont-Blanc prototype (both mobile processors and ARM server chips)
  • To provide continued support for the Mont-Blanc consortium, namely operations of the Mont-Blanc prototype, and hands-on support for the application developers

The extension of Mont-Blanc contributes to the development of extreme scale energy-efficient platforms, with potential for Exascale computing, addressing the challenges of massive parallelism, heterogeneous computing, and resiliency. This second phase of the project has a great potential to create new market opportunities for sucessful EC technology, by placing embedded architectures in servers and HPC.

The third phase of the Mont-Blanc project, running from 2015 to 2018, builds upon the previous Mont-Blanc & Mont-Blanc 2 FP7 projects, with ARM, BSC & Bull being involved in all three projects. It adopts a co-design approach to ensure that hardware and system innovations are readily translated into benefits for HPC applications. It aims at designing a new high-end HPC platform that is able to deliver a new level of performance / energy ratio when executing real applications. This encompasses the three following objectives:

  • To design a well-balanced architecture and to deliver the design for an ARM based SoC (System-on-a-Chip) or SoP (System-on-Package) capable of providing pre-exascale performance when implemented in the 2019-2020time frame. The predicted performance target must be measured using real HPC applications.
  • To maximise the benefit for HPC applications with new high-performance ARM processors and throughput-oriented compute accelerators designed to work together.
  • To develop the necessary software ecosystem for the future SoC. This additional objective is key to ensure that the project successfully translates into an industrial offer for the HPC market.