When citing the Mont-Blanc project, we would be grateful if you could cite our paper "SUPERCOMPUTING WITH COMMODITY CPUS: ARE MOBILE SOCS READY FOR HPC?", winner of the Best Student Paper Award during the 2013 edition of the Supercomputing Conference.

Found 115 results
Conference Proceedings
E. D. C. Francesquini, Castro, M. B., Nguélé, T. M., and Mehaut, J. - F., Analysis of Computing and Energy Performance of Multicore, NUMA, and Manycore Platforms for an Irregular Applications, SC13, Denver. 2013.
B. Videau, Marangozova-Martin, V., and Cronsioe, J., BOAST: Bringing Optimization through Automatic Source-to-Source Tranformations, Tokyo, Japan. 2013.
P. Fuentes, Bosque, J. Luis, Beivide, R., Valero, M., and Minkenberg, C., Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster. In Proceedings of the 2014 IEEE/ACM International Symposium on Big Data Computing (BDC '14), 2014.
I. Tanasic, Vilanova, L., Jordà, M., Cabezas, J., Gelado, I., Navarro, N., and Hwu, W. -mei, Comparison based sorting for systems with multiple GPUs, Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units: ACM. pp. pp. 1–11, 2013.
R. Hunt and McIntosh-Smith, S., Exploiting spatial information in datasets to enable fault tolerant sparse matrix solvers. Fault Tolerant Systems Workshop at IEEE Cluster 2015, 2015.
M. Benito, Vallejo, E., Beivide, R., and Izu, C., Extending commodity OpenFlow switches for large-scale HPC deployments. 2017 IEEE 3rd International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB), Austin, Texas, USA, 2017.
L. Stanisic, Videau, B., Cronsioe, J., Degomme, A., Marangozova-Martin, V., Legrand, A., and Mehaut, J. - F., Performance Analysis of HPC Applications on Low-Power Embedded Platforms. Proceedings of the Conference on Design, Automation, Test in Europe (DATE'13). 2013.
C. Camarero, Martínez, C., and Beivide, R., Random Folded Clos Topologies for Datacenter Networks. 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, Texas, USA, 2017.
R. Garibotti, Ost, L., Busseuil, R., kourouma, M., Adeniyi-Jones, C., and Sassatelli, G., Simultaneous multithreading support in embedded distributed memory MPSoCs. ACM,, 2013.
E. Stafford, Pérez, B., Bosque, J. Luis, Beivide, R., and Valero, M., To distribute or not to distribute: the question of load balancing for performance or energy. Springer, Cham, Euro-Par 2017: Parallel Processing, Santiago de Compostela, pp. 710-722, 2017.
International Conferences
I. Pérez, Castillo, E., Beivide, R., Vallejo, E., Bosque, J. Luis, Moreto, M., Casas, M., and Valero, M., Analyzing the Impact of Parallel Programming Models in NoCs of Forthcoming CMP Architectures. Proceedings of the EMerging Technology (EMiT) Conference, Barcelona, Spain, 2016.
S. McIntosh-Smith, Hunt, R., Price, J., and Vesztrocy, A., Application-Based Fault Tolerance Techniques for Sparse Matrix Solvers. International Journal of High Performance Computing Applications, 2016.
J. Gracia and Zhou, H., Asynchronous progress design for a MPI-based PGAS one-sided communication system. 22nd IEEE International Conference on Parallel and Distributed Systems (ICPADS 2016), Wuhan, China, 2016.
E. Castillo, Moreto, M., Casas, M., Alvarez, L., Vallejoz, E., Chronaki, K., Badia, R., Bosquez, J. Luis, Beividez, R., Ayguadé, E., Labarta, J., and Valero, M., CATA: Criticality Aware Task Acceleration for Multicore Processors. International Parallel and Distributed Parallel Symposium (IPDPS) 2016, Chicago, USA, 2016.
P. Fuentes, Vallejo, E., García, M., Beivide, R., Rodríguez, G., Minkenberg, C., and Valero, M., Contention-based Nonminimal Adaptive Routing in High-radix Networks. 29th IEEE International Parallel & Distributed Processing Symposium, India, 2015.
K. Chronaki, Rico, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures, ICS '15: Internationcal Conference in Supercomputing. 2015.
M. Pavlovic, Puzovic, N., and Ramirez, A., Data Placement in HPC Architectures with Heterogeneous Off-chip Memory. 2013.
A. Butko, Gamatié, A., G., S., Torres, L., and Robert, M., Design Exploration For Next Generation High-Performance Manycore On-chip Systems: Application To big.LITTLE Architectures. In 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.
B. Pérez, Stafford, E., Bosque, J. Luis, and Beivide, R., Energy Efficiency Evaluation in Heterogeneous Computers. Barcelona, Spain, Proceedings of the EMerging Technology (EMiT) Conference, 2016.
B. Pérez, Stafford, E., Bosque, J. Luis, and Beivide, R., Energy efficiency of load balancing for data-parallel applications in heterogeneous systems. Proceedings of the 16th International Conference on Computational and Mathematical Methods in Science and Engineering, Cádiz, Spain, 2016.