When citing the Mont-Blanc project, we would be grateful if you could cite our paper "SUPERCOMPUTING WITH COMMODITY CPUS: ARE MOBILE SOCS READY FOR HPC?", winner of the Best Student Paper Award during the 2013 edition of the Supercomputing Conference.

Found 115 results
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L. Backes, Rico, A., and Franke, B., Experiences in Speeding Up Computer Vision Applications on Mobile Computing Platforms, 2015.
L. Bautista-Gomez, Zyulkyarov, F., McIntosh-Smith, S., and Unsal, O. S., UNPROTECTED COMPUTING : A LARGE-SCALE STUDY OF DRAM RAW ERROR RATE ON A SUPERCOMPUTER, 2016.
M. Benito, Vallejo, E., and Beivide, R., On the Use of Commodity Ethernet Technology in Exascale HPC Systems, presented at the 12/2015, Bangalore, India, 2015.
M. Benito, Vallejo, E., Beivide, R., and Izu, C., Extending commodity OpenFlow switches for large-scale HPC deployments. 2017 IEEE 3rd International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB), Austin, Texas, USA, 2017.
D. Broemmel, Experience with StarSS­ -- off and on a GPU, Porting large production codes to SMPSs/OmpSs, CECAM Workshop: Exploiting heterogeneous multi-core and many-core platforms for atomic and molecular simulations, Daresbury, September 10-12, 2014. 2014.
A. Butko, Garibotti, R., Ost, L., Lapôtre, V., Gamatié, A., G., S., and Adeniyi-Jones, C., A Trace-driven Approach for Fast and Accurate Simulation of Manycore Architectures. 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015.
A. Butko, Gamatié, A., G., S., Torres, L., and Robert, M., Design Exploration For Next Generation High-Performance Manycore On-chip Systems: Application To big.LITTLE Architectures. In 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.
A. Butko, Bruguier, F., Gamatie, A., and Sassatelli, G., Efficient Programming for Multicore Processor Heterogeneity: OpenMP versus OmpSs. OpenSuCo workshop, ISC 2017, Frankfurt, Germany, 2017.
A. Butko, Bessad, L., Gamatié, A., Sassatelli, G., Torres, L., and Robert, M., Position Paper: OpenMP scheduling on ARM big.LITTLE architecture. In Ninth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016), 2016.
A. Butko, BRUGUIER, F., Gamatié, A., Sassatelli, G., NOVO, D., Torres, L., and Robert, M., Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration, 21-23 september 2016. IEEE MCSoC : International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016.
C. Camarero, Martínez, C., and Beivide, R., Random Folded Clos Topologies for Datacenter Networks. 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, Texas, USA, 2017.
C. Camarero, Martínez, C., Vallejo, E., and Beivide, R., Projective Networks: Topologies for Large Parallel Computer Systems. IEEE Computer Society, IEEE Transactions on Parallel and Distributed Systems.
C. Camarero, Vallejo, E., and Beivide, R., Topological Characterization of Hamming and Dragonfly Networks and Its Implications on Routing, vol. Volume 11, no. Issue 4. ACM Transactions on Architecture and Code Optimization (TACO), 2015.
P. Carpenter, Building supercomputers from commodity embedded chips. 2014.
P. Carpenter, European scalable and power efficient HPC platform based on low-power embedded technology. ISCA 2013, 2013.
E. Castillo, Moreto, M., Casas, M., Alvarez, L., Vallejoz, E., Chronaki, K., Badia, R., Bosquez, J. Luis, Beividez, R., Ayguadé, E., Labarta, J., and Valero, M., CATA: Criticality Aware Task Acceleration for Multicore Processors. International Parallel and Distributed Parallel Symposium (IPDPS) 2016, Chicago, USA, 2016.
M. Castro, Francesquini, E., Dupros, F., Aochi, H., Navaux, P., and Méhaut, J. - F., Seismic Wave Propagation on Low-Power and Performance-centric Manycores. Elsevier, Journal of Parallel Computing (ParCO), 2016.
K. Chronaki, Rico, A., Casas, M., Planas, M. Moreto, Sala, R. Maria Badi, Parra, E. Ayguadé, Mancho, J. José Laba, and Cortés, M. Valero, Task scheduling techniques for asymmetric multi-core systems, 2017.
K. Chronaki, Rico, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures.
K. Chronaki, Rico, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures, ICS '15: Internationcal Conference in Supercomputing. 2015.